1. Field of the Invention
Embodiments of the present invention relate generally to integrated circuit design and more specifically to a long-distance synchronous bus.
2. Description of the Related Art
Complex integrated circuit designs are typically comprised of a plurality of logic blocks. As is often the case, a first logic block transmits data to a second logic block. There are several established methods of data flow control that are used in cases when the second logic block cannot always accept the data from the first logic block. One such method uses a valid and a busy signal. The valid signal is transmitted with the data and, when asserted, indicates to the second block that the data arriving at the second block is valid (i.e., should be accepted). The busy signal is asserted by the second logic block to indicate to the first logic block the second logic block cannot currently accept data. The first logic block responds by not transmitting any additional data until the busy signal is de-asserted.
For this method of flow control to work properly, there cannot be any excessive latency in the timing of the busy and valid signals. For example, assuming a synchronous system, the busy signal must be received by the first logic block within the same clock cycle as the data being currently being transmitted. If the busy signal is not received within the same clock cycle, then the data may be lost since the first logic block ends up sending the data when the second logic block is not accepting data. The timing requirements of the valid and busy signals limit the distance that the first logic block may transmit data to the second logic block to approximately the distance that a signal propagates during one-half a clock cycle.
In view of flow control signal timing requirements, one or more retiming stages may be used between logic blocks to increase the distance data can be transmitted. Generally, a retiming stage receives a data packet and a corresponding valid signal from a first logic block and then transmits both to a second logic block so long as the second logic block has not sent a busy signal to the first logic block. In a synchronous system, the signals and data packet are typically received by flops clocked by a clock signal. Since the valid and busy signals are timing critical signals, the retiming stage includes additional logic to decouple the valid and busy signals from the first logic block and the second logic block. The decoupling allows a busy signal sent from the second logic block to be detected so that a data packet transmitted by the first logic block can be held until the busy signal has cleared.
One drawback to this approach is that the additional logic adds propagation delays to the valid and busy signals. As is well-known, the distance that a signal travels between a first logic block and a second logic block during a clock cycle may be determined using a timing budget, where the sum of the propagation delays of the signal through system elements, such as logic components, and the propagation delay of the signal in the wire(s) between the first and second logic blocks is equal to the clock period. When a retiming stage disposed between the first and second logic blocks includes additional logic, the propagation delays through the additional logic reduce the amount of time left in the clock cycle for the signal to propagate through the wire(s) between the first and second logic blocks. Thus, the signal does is unable to travel as far during each clock cycle. Since the distance traveled is reduced, more retiming stages may be required between the first logic block and the second logic block, leading to increased design complexity and retiming stage area requirements.
Another drawback is that a logic designer may try to anticipate timing problems caused by long data paths between logic blocks by inserting retiming stages into the initial hardware design. However, if a retiming stage is not needed in the final design, then the overall design is burdened with excess logic, which unnecessarily consumes die area.
These drawbacks are exacerbated in cases where a sending logic block transmits data to more than one receiving logic block.
As the foregoing illustrates, what is needed in the art is a more flexible bus design that implements simpler retiming stages.